大葉大學圖書館 |

登入

回首頁

A Structured Design Methodology for ...

Arizona State University.

A Structured Design Methodology for High Performance VLSI Arrays.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
書名/作者:	A Structured Design Methodology for High Performance VLSI Arrays.
作者:	Maurya, Satendra.
面頁冊數:	147 p.
附註:	Source: Dissertation Abstracts International, Volume: 73-08(E), Section: B, page: .
Contained By:	Dissertation Abstracts International73-08(E)B.
標題:	Design and Decorative Arts.
標題:	Engineering, Electronics and Electrical.
ISBN:	9781267296429
摘要、提要註:	The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market with high reliability and performance is one of the most competitive challenges. Both custom and ASIC design methodologies have evolved over the time to cope with this but the high manual labor in custom and statistic design in ASIC are still causes of concern.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3505389

A Structured Design Methodology for High Performance VLSI Arrays.
Maurya, Satendra.

A Structured Design Methodology for High Performance VLSI Arrays. - 147 p.

Source: Dissertation Abstracts International, Volume: 73-08(E), Section: B, page: .

Thesis (Ph.D.)--Arizona State University, 2012.

The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market with high reliability and performance is one of the most competitive challenges. Both custom and ASIC design methodologies have evolved over the time to cope with this but the high manual labor in custom and statistic design in ASIC are still causes of concern.

ISBN: 9781267296429Subjects--Topical Terms:

423076
Design and Decorative Arts.

A Structured Design Methodology for High Performance VLSI Arrays.
LDR:02615nam 2200337 4500 001 377879
005 20130403093048.5
008 130522s2012 ||||||||||||||||| ||eng d
020 $a 9781267296429
035 $a (UMI)AAI3505389
035 $a AAI3505389
040 $a UMI $c UMI
100 1 $a Maurya, Satendra. $3 506783
245 1 2 $a A Structured Design Methodology for High Performance VLSI Arrays.
300 $a 147 p.
500 $a Source: Dissertation Abstracts International, Volume: 73-08(E), Section: B, page: .
500 $a Adviser: Lawrence T. Clark.
502 $a Thesis (Ph.D.)--Arizona State University, 2012.
520 $a The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market with high reliability and performance is one of the most competitive challenges. Both custom and ASIC design methodologies have evolved over the time to cope with this but the high manual labor in custom and statistic design in ASIC are still causes of concern.
520 $a This work proposes a new circuit design strategy that focuses mostly on arrayed structures like TLB, RF, Cache, IPCAM etc. that reduces the manual effort to a great extent and also makes the design regular, repetitive still achieving high performance. The method proposes making the complete design custom schematic but using the standard cells. This requires adding some custom cells to the already exhaustive library to optimize the design for performance. Once schematic is finalized, the designer places these standard cells in a spreadsheet, placing closely the cells in the critical paths. A Perl script then generates Cadence Encounter compatible placement file. The design is then routed in Encounter. Since designer is the best judge of the circuit architecture, placement by the designer will allow achieve most optimal design.
520 $a Several designs like IPCAM, issue logic, TLB, RF and Cache designs were carried out and the performance were compared against the fully custom and ASIC flow. The TLB, RF and Cache were the part of the HEMES microprocessor.
590 $a School code: 0010.
650 4 $a Design and Decorative Arts. $3 423076
650 4 $a Engineering, Electronics and Electrical. $3 422945
690 $a 0389
690 $a 0544
710 2 $a Arizona State University. $b Electrical Engineering. $3 506784
773 0 $t Dissertation Abstracts International $g 73-08(E)B.
790 1 0 $a Clark, Lawrence T., $e advisor
790 1 0 $a Holbert, Keith $e committee member
790 1 0 $a Vrudhula, Sarma $e committee member
790 1 0 $a Allee, David $e committee member
790 $a 0010
791 $a Ph.D.
792 $a 2012
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3505389

筆 0 讀者評論

多媒體

多媒體檔案
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3505389

評論

新增評論分享你的心得

Export

取書館別