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Architectural Techniques for Memory Oversight in Multiprocessors.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
書名/作者:	Architectural Techniques for Memory Oversight in Multiprocessors.
作者:	Shriraman, Arrvindh.
面頁冊數:	213 p.
附註:	Source: Dissertation Abstracts International, Volume: 72-04, Section: B, page: 2214.
Contained By:	Dissertation Abstracts International72-04B.
標題:	Engineering, Electronics and Electrical.
標題:	Computer Science.
ISBN:	9781124481906
摘要、提要註:	Computer architects have exploited the transistors afforded by Moore's law to provide software developers with high performance computing resources. Software has translated this growth in hardware resources into improved features and applications. Unfortunately, applications have become increasingly complex and are prone to a variety of bugs when multiple software modules interact. The advent of multicore processors introduces a new challenge, parallel programming, which requires programmers to coordinate multiple tasks.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3442780

Architectural Techniques for Memory Oversight in Multiprocessors.
Shriraman, Arrvindh.

Architectural Techniques for Memory Oversight in Multiprocessors. - 213 p.

Source: Dissertation Abstracts International, Volume: 72-04, Section: B, page: 2214.

Thesis (Ph.D.)--University of Rochester, 2011.

Computer architects have exploited the transistors afforded by Moore's law to provide software developers with high performance computing resources. Software has translated this growth in hardware resources into improved features and applications. Unfortunately, applications have become increasingly complex and are prone to a variety of bugs when multiple software modules interact. The advent of multicore processors introduces a new challenge, parallel programming, which requires programmers to coordinate multiple tasks.

ISBN: 9781124481906Subjects--Topical Terms:

422945
Engineering, Electronics and Electrical.

Architectural Techniques for Memory Oversight in Multiprocessors.
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245 1 0 $a Architectural Techniques for Memory Oversight in Multiprocessors.
300 $a 213 p.
500 $a Source: Dissertation Abstracts International, Volume: 72-04, Section: B, page: 2214.
500 $a Adviser: Sandhya Durarkadas.
502 $a Thesis (Ph.D.)--University of Rochester, 2011.
520 $a Computer architects have exploited the transistors afforded by Moore's law to provide software developers with high performance computing resources. Software has translated this growth in hardware resources into improved features and applications. Unfortunately, applications have become increasingly complex and are prone to a variety of bugs when multiple software modules interact. The advent of multicore processors introduces a new challenge, parallel programming, which requires programmers to coordinate multiple tasks.
520 $a This dissertation develops general-purpose hardware mechanisms that address the dual challenges of parallel programming and software reliability. We have devised hardware mechanisms in the memory hierarchy that shed light on the memory system and control the visibility of data among the multiple threads. The key novelty is the use of cache coherence protocols to implement hardware mechanisms that enable software to track and regulate memory accesses at cache-line granularity. We demonstrate that exposing the events in the memory hierarchy provides useful information that was either previously invisible to software or would have required heavyweight instrumentation.
520 $a Focusing on the challenge of parallel programming, our mechanisms aid implementations of Transactional Memory (TM), a programming construct that seeks to simplify synchronization of shared state. We develop two mechanisms, Alert-On-Update (AOU) and Programmable Data Isolation (PDI), to accelerate common TM tasks. AOU selectively exposes cache events, including those that are triggered by remote accesses, to software in the form of events. TM runtimes use it to detect accesses that overlap between transactions (i.e., conflicts), and track a transaction's status. Programmable-Data-Isolation (PDI) allows multiple threads to temporarily hide their speculative writes from concurrent threads in their private caches until software decides to make them visible. We have used PDI and AOU to implement two TM run-time systems, RTM and FIexTM. Both RTM and FlexTM are flexible runtimes that permit software control of the timing of conflict resolution and the policy used for conflict management.
520 $a To address the challenge of software reliability, we propose Sentry, a lightweight, flexible access-control mechanism. Sentry allows software to regulate the reads and writes to memory regions at cache-line granularity based on the context in the program. Sentry coordinates the coherence states in a novel manner to eliminate the need for permission checks entirely for a large majority of the program's accesses (all cache hits), thereby improving efficiency. Sentry improves application reliability by regulating data visibility and movement among the multiple software modules present in the application. We use a real-world webserver, Apache, as a case study to illustrate Sentry's ability to guard the core application from vulnerabilities in the application's modules.
590 $a School code: 0188.
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650 4 $a Computer Science. $3 423143
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710 2 $a University of Rochester. $3 475298
773 0 $t Dissertation Abstracts International $g 72-04B.
790 1 0 $a Durarkadas, Sandhya, $e advisor
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791 $a Ph.D.
792 $a 2011
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