大葉大學圖書館 |

General-purpose graphics processor architectures /

紀錄類型:	書目-電子資源 : Monograph/item
杜威分類號:	006.6869
書名/作者:	General-purpose graphics processor architectures // Tor M. Aamodt, Wilson Wai Lun Fung, Timothy G. Rogers.
作者:	Aamodt, Tor M.,
其他作者:	Fung, Wilson Wai Lun,
出版者:	[San Rafael, California] : : Morgan & Claypool,, 2018.
面頁冊數:	1 PDF (xvii, 122 pages) : : illustrations.
附註:	Part of: Synthesis digital library of engineering and computer science.
標題:	Graphics processing units.
標題:	Computer architecture.
ISBN:	9781627056182
書目註:	Includes bibliographical references (pages 103-119).
內容註:	1. Introduction -- 1.1 The landscape of computation accelerators -- 1.2 GPU hardware basics -- 1.3 A brief history of GPUs -- 1.4 Book outline --
摘要、提要註:	Originally developed to support video games, graphics processor units (GPUs) are now increasingly used for general-purpose (non-graphics) applications ranging from machine learning to mining of cryptographic currencies. GPUs can achieve improved performance and efficiency versus central processing units (CPUs) by dedicating a larger fraction of hardware resources to computation. In addition, their general-purpose programmability makes contemporary GPUs appealing to software developers in comparison to domain-specific accelerators. This book provides an introduction to those interested in studying the architecture of GPUs that support general-purpose computing. It collects together information currently only found among a wide range of disparate sources. The authors led development of the GPGPU-Sim simulator widely used in academic research on GPU architectures. The first chapter of this book describes the basic hardware structure of GPUs and provides a brief overview of their history. Chapter 2 provides a summary of GPU programming models relevant to the rest of the book. Chapter 3 explores the architecture of GPU compute cores. Chapter 4 explores the architecture of the GPU memory system. After describing the architecture of existing systems, Chapters 3 and 4 provide an overview of related research. Chapter 5 summarizes cross-cutting research impacting both the compute core and memory system. This book should provide a valuable resource for those wishing to understand the architecture of graphics processor units (GPUs) used for acceleration of general-purpose applications and to those who want to obtain an introduction to the rapidly growing body of research exploring how to improve the architecture of these GPUs.
電子資源:	https://ieeexplore.ieee.org/servlet/opac?bknumber=8363085

General-purpose graphics processor architectures /
Aamodt, Tor M.,

General-purpose graphics processor architectures /Tor M. Aamodt, Wilson Wai Lun Fung, Timothy G. Rogers. - [San Rafael, California] :Morgan & Claypool,2018. - 1 PDF (xvii, 122 pages) :illustrations. - Synthesis lectures on computer architecture,# 441935-3243 ;. - Synthesis digital library of engineering and computer science..

Part of: Synthesis digital library of engineering and computer science.

Includes bibliographical references (pages 103-119).

1. Introduction -- 1.1 The landscape of computation accelerators -- 1.2 GPU hardware basics -- 1.3 A brief history of GPUs -- 1.4 Book outline --

Abstract freely available; full-text restricted to subscribers or individual document purchasers.

Compendex

Originally developed to support video games, graphics processor units (GPUs) are now increasingly used for general-purpose (non-graphics) applications ranging from machine learning to mining of cryptographic currencies. GPUs can achieve improved performance and efficiency versus central processing units (CPUs) by dedicating a larger fraction of hardware resources to computation. In addition, their general-purpose programmability makes contemporary GPUs appealing to software developers in comparison to domain-specific accelerators. This book provides an introduction to those interested in studying the architecture of GPUs that support general-purpose computing. It collects together information currently only found among a wide range of disparate sources. The authors led development of the GPGPU-Sim simulator widely used in academic research on GPU architectures. The first chapter of this book describes the basic hardware structure of GPUs and provides a brief overview of their history. Chapter 2 provides a summary of GPU programming models relevant to the rest of the book. Chapter 3 explores the architecture of GPU compute cores. Chapter 4 explores the architecture of the GPU memory system. After describing the architecture of existing systems, Chapters 3 and 4 provide an overview of related research. Chapter 5 summarizes cross-cutting research impacting both the compute core and memory system. This book should provide a valuable resource for those wishing to understand the architecture of graphics processor units (GPUs) used for acceleration of general-purpose applications and to those who want to obtain an introduction to the rapidly growing body of research exploring how to improve the architecture of these GPUs.

Mode of access: World Wide Web.

ISBN: 9781627056182

Standard No.: 10.2200/S00848ED1V01Y201804CAC044doiSubjects--Topical Terms:

600689
Graphics processing units.
Subjects--Index Terms:

GPGPUIndex Terms--Genre/Form:

336502
Electronic books.

LC Class. No.: T385 / .A243 2018

Dewey Class. No.: 006.6869

General-purpose graphics processor architectures /
LDR:06264nmm 2200553 i 4500 001 509525
003 IEEE
005 20180526172127.0
006 m eo d
007 cr cn |||m|||a
008 210524s2018 caua foab 000 0 eng d
020 $a 9781627056182 $q ebook
020 $z 9781627059237 $q paperback
020 $z 9781681733586 $q hardcover
024 7 $a 10.2200/S00848ED1V01Y201804CAC044 $2 doi
035 $a (CaBNVSL)swl408345
035 $a (OCoLC)1037800609
035 $a 8363085
040 $a CaBNVSL $b eng $e rda $c CaBNVSL $d CaBNVSL
050 4 $a T385 $b .A243 2018
082 0 4 $a 006.6869 $2 23
100 1 $a Aamodt, Tor M., $e author. $3 729066
245 1 0 $a General-purpose graphics processor architectures / $c Tor M. Aamodt, Wilson Wai Lun Fung, Timothy G. Rogers.
260 1 $a [San Rafael, California] : $b Morgan & Claypool, $c 2018.
264 1 $a [San Rafael, California] : $b Morgan & Claypool, $c 2018.
300 $a 1 PDF (xvii, 122 pages) : $b illustrations.
336 $a text $2 rdacontent
337 $a electronic $2 isbdmedia
338 $a online resource $2 rdacarrier
490 1 $a Synthesis lectures on computer architecture, $x 1935-3243 ; $v # 44
500 $a Part of: Synthesis digital library of engineering and computer science.
504 $a Includes bibliographical references (pages 103-119).
505 0 $a 1. Introduction -- 1.1 The landscape of computation accelerators -- 1.2 GPU hardware basics -- 1.3 A brief history of GPUs -- 1.4 Book outline --
505 8 $a 2. Programming model -- 2.1 Execution model -- 2.2 GPU instruction set architectures -- 2.2.1 NVIDIA GPU instruction set architectures -- 2.2.2 AMD graphics core next instruction set architecture --
505 8 $a 3. The SIMT core: instruction and register data flow -- 3.1 One-loop approximation -- 3.1.1 SIMT execution masking -- 3.1.2 SIMT deadlock and stackless SIMT architectures -- 3.1.3 Warp scheduling -- 3.2 Two-loop approximation -- 3.3 Three-loop approximation -- 3.3.1 Operand collector -- 3.3.2 Instruction replay: handling structural hazards -- 3.4 Research directions on branch divergence -- 3.4.1 Warp compaction -- 3.4.2 Intra-warp divergent path management -- 3.4.3 Adding MIMD capability -- 3.4.4 Complexity-effective divergence management -- 3.5 Research directions on scalarization and affine execution -- 3.5.1 Detection of uniform or affine variables -- 3.5.2 Exploiting uniform or affine variables in GPU -- 3.6 Research directions on register file architecture -- 3.6.1 Hierarchical register file -- 3.6.2 Drowsy state register file -- 3.6.3 Register file virtualization -- 3.6.4 Partitioned register file -- 3.6.5 RegLess --
505 8 $a 4. Memory system -- 4.1 First-level memory structures -- 4.1.1 Scratchpad memory and L1 data cache -- 4.1.2 L1 texture cache -- 4.1.3 Unified texture and data cache -- 4.2 On-chip interconnection network -- 4.3 Memory partition unit -- 4.3.1 L2 cache -- 4.3.2 Atomic operations -- 4.3.3 Memory access scheduler -- 4.4 Research directions for GPU memory systems -- 4.4.1 Memory access scheduling and interconnection network design -- 4.4.2 Caching effectiveness -- 4.4.3 Memory request prioritization and cache bypassing -- 4.4.4 Exploiting inter-warp heterogeneity -- 4.4.5 Coordinated cache bypassing -- 4.4.6 Adaptive cache management -- 4.4.7 Cache prioritization -- 4.4.8 Virtual memory page placement -- 4.4.9 Data placement -- 4.4.10 Multi-chip-module GPUs --
505 8 $a 5. Crosscutting research on GPU computing architectures -- 5.1 Thread scheduling -- 5.1.1 Research on assignment of threadblocks to cores -- 5.1.2 Research on cycle-by-cycle scheduling decisions -- 5.1.3 Research on scheduling multiple kernels -- 5.1.4 Fine-grain synchronization aware scheduling -- 5.2 Alternative ways of expressing parallelism -- 5.3 Support for transactional memory -- 5.3.1 Kilo TM -- 5.3.2 Warp TM and temporal conflict detection -- 5.4 Heterogeneous systems --
505 8 $a Bibliography -- Authors' biographies.
506 $a Abstract freely available; full-text restricted to subscribers or individual document purchasers.
510 0 $a Compendex
510 0 $a INSPEC
510 0 $a Google scholar
510 0 $a Google book search
520 3 $a Originally developed to support video games, graphics processor units (GPUs) are now increasingly used for general-purpose (non-graphics) applications ranging from machine learning to mining of cryptographic currencies. GPUs can achieve improved performance and efficiency versus central processing units (CPUs) by dedicating a larger fraction of hardware resources to computation. In addition, their general-purpose programmability makes contemporary GPUs appealing to software developers in comparison to domain-specific accelerators. This book provides an introduction to those interested in studying the architecture of GPUs that support general-purpose computing. It collects together information currently only found among a wide range of disparate sources. The authors led development of the GPGPU-Sim simulator widely used in academic research on GPU architectures. The first chapter of this book describes the basic hardware structure of GPUs and provides a brief overview of their history. Chapter 2 provides a summary of GPU programming models relevant to the rest of the book. Chapter 3 explores the architecture of GPU compute cores. Chapter 4 explores the architecture of the GPU memory system. After describing the architecture of existing systems, Chapters 3 and 4 provide an overview of related research. Chapter 5 summarizes cross-cutting research impacting both the compute core and memory system. This book should provide a valuable resource for those wishing to understand the architecture of graphics processor units (GPUs) used for acceleration of general-purpose applications and to those who want to obtain an introduction to the rapidly growing body of research exploring how to improve the architecture of these GPUs.
530 $a Also available in print.
538 $a Mode of access: World Wide Web.
588 $a Title from PDF title page (viewed on May 25, 2018).
650 0 $a Graphics processing units. $3 600689
650 0 $a Computer architecture. $3 172048
653 $a GPGPU
653 $a Computer architecture
655 0 $a Electronic books. $2 local $3 336502
700 1 $a Fung, Wilson Wai Lun, $e author. $3 729067
700 1 $a Rogers, Timothy G., $e author. $3 729068
776 0 8 $i Print version: $z 9781627059237 $z 9781681733586
830 0 $a Synthesis digital library of engineering and computer science. $3 461208
830 0 $a Synthesis lectures in computer architecture ; $v #13. $3 628438
856 4 2 $3 Abstract with links to resource $u https://ieeexplore.ieee.org/servlet/opac?bknumber=8363085