Principles of secure processor archi...
Szefer, Jakub,

 

  • Principles of secure processor architecture design /
  • 紀錄類型: 書目-電子資源 : Monograph/item
    杜威分類號: 004.22
    書名/作者: Principles of secure processor architecture design // Jakub Szefer.
    作者: Szefer, Jakub,
    出版者: [San Rafael, California] : : Morgan & Claypool,, 2019.
    面頁冊數: 1 PDF (xxi, 151 pages) : : illustrations.
    附註: Part of: Synthesis digital library of engineering and computer science.
    標題: Computer architecture.
    標題: Computer security.
    ISBN: 9781681730028
    書目註: Includes bibliographical references (pages 125-148).
    內容註: Bibliography -- Online resources -- Author's biography.
    摘要、提要註: With growing interest in computer security and the protection of the code and data which execute on commodity computers, the amount of hardware security features in today's processors has increased significantly over the recent years. No longer of just academic interest, security features inside processors have been embraced by industry as well, with a number of commercial secure processor architectures available today. This book aims to give readers insights into the principles behind the design of academic and commercial secure processor architectures. Secure processor architecture research is concerned with exploring and designing hardware features inside computer processors, features which can help protect confidentiality and integrity of the code and data executing on the processor. Unlike traditional processor architecture research that focuses on performance, efficiency, and energy as the first-order design objectives, secure processor architecture design has security as the first-order design objective (while still keeping the others as important design aspects that need to be considered). This book aims to present the different challenges of secure processor architecture design to graduate students interested in research on architecture and hardware security and computer architects working in industry interested in adding security features to their designs. It aims to educate readers about how the different challenges have been solved in the past and what are the best practices, i.e., the principles, for design of new secure processor architectures. Based on the careful review of past work by many computer architects and security researchers, readers also will come to know the five basic principles needed for secure processor architecture design. The book also presents existing research challenges and potential new research directions. Finally, this book presents numerous design suggestions, as well as discusses pitfalls and fallacies that designers should avoid.
    電子資源: https://ieeexplore.ieee.org/servlet/opac?bknumber=8502017
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