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Productive Design of Extensible On-C...

Cook, Henry Michael.

Productive Design of Extensible On-Chip Memory Hierarchies.

紀錄類型:	書目-電子資源 : Monograph/item
書名/作者:	Productive Design of Extensible On-Chip Memory Hierarchies.
作者:	Cook, Henry Michael.
出版者:	Ann Arbor : : ProQuest Dissertations & Theses, , 2016
面頁冊數:	153 p.
附註:	Source: Dissertation Abstracts International, Volume: 77-12(E), Section: B.
Contained By:	Dissertation Abstracts International77-12B(E).
標題:	Computer science.
標題:	Computer engineering.
ISBN:	9781369057065
摘要、提要註:	As Moore's Law slows and process scaling yields only small returns, computer architecture and design are poised to undergo a renaissance. This thesis brings the productivity of modern software tools to bear on the design of future energy-efficient hardware architectures.

Productive Design of Extensible On-Chip Memory Hierarchies.
Cook, Henry Michael.

Productive Design of Extensible On-Chip Memory Hierarchies. - Ann Arbor : ProQuest Dissertations & Theses, 2016 - 153 p.

Source: Dissertation Abstracts International, Volume: 77-12(E), Section: B.

Thesis (Ph.D.)--University of California, Berkeley, 2016.

As Moore's Law slows and process scaling yields only small returns, computer architecture and design are poised to undergo a renaissance. This thesis brings the productivity of modern software tools to bear on the design of future energy-efficient hardware architectures.

ISBN: 9781369057065Subjects--Topical Terms:

182962
Computer science.

Productive Design of Extensible On-Chip Memory Hierarchies.
LDR:02409nmm a2200313 4500 001 476247
005 20170614101408.5
008 181208s2016 ||||||||||||||||| ||eng d
020 $a 9781369057065
035 $a (MiAaPQ)AAI10150942
035 $a AAI10150942
040 $a MiAaPQ $c MiAaPQ
100 1 $a Cook, Henry Michael. $3 686836
245 1 0 $a Productive Design of Extensible On-Chip Memory Hierarchies.
260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2016
300 $a 153 p.
500 $a Source: Dissertation Abstracts International, Volume: 77-12(E), Section: B.
500 $a Adviser: David Patterson.
502 $a Thesis (Ph.D.)--University of California, Berkeley, 2016.
520 $a As Moore's Law slows and process scaling yields only small returns, computer architecture and design are poised to undergo a renaissance. This thesis brings the productivity of modern software tools to bear on the design of future energy-efficient hardware architectures.
520 $a In particular, it targets one of the most difficult design tasks in the hardware domain: Coherent hierarchies of on-chip caches. I have extended the capabilities of Chisel, a new hardware description language, by providing libraries for hardware developers to use to describe the configuration and behavior of such memory hierarchies, with a focus on the cache coherence protocols that work behind the scenes to preserve their abstraction of global shared memory. I discuss how the methods I provide enable productive and extensible memory hierarchy design by separating the concerns of different hierarchy components, and I explain how this forms the basis for a generative approach to agile hardware design.
520 $a This thesis describes a general framework for context-dependent parameterization of any hardware generator, defines a specific set of Chisel libraries for generating extensible cache-coherent memory hierarchies, and provides a methodology for decomposing high-level descriptions of cache coherence protocols into controller-localized, object-oriented transactions.
520 $a This methodology has been used to generate the memory hierarchies of a lineage of RISC-V chips fabricated as part of the ASPIRE Lab's investigations into application-specific processor design.
590 $a School code: 0028.
650 4 $a Computer science. $3 182962
650 4 $a Computer engineering. $3 411802
690 $a 0984
690 $a 0464
710 2 0 $a University of California, Berkeley. $b Electrical Engineering and Computer Sciences. $3 686837
773 0 $t Dissertation Abstracts International $g 77-12B(E).
790 $a 0028
791 $a Ph.D.
792 $a 2016
793 $a English

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