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IP cores design from specifications ...

Mohamed, Khaled Salah.

IP cores design from specifications to production[electronic resource] :modeling, verification, optimization, and protection /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
杜威分類號:	621.395
書名/作者:	IP cores design from specifications to production : modeling, verification, optimization, and protection // by Khaled Salah Mohamed.
作者:	Mohamed, Khaled Salah.
出版者:	Cham : : Springer International Publishing :, 2016.
面頁冊數:	ix, 154 p. : : ill., digital ;; 24 cm.
Contained By:	Springer eBooks
標題:	Integrated circuits - Very large scale integration.
標題:	Engineering.
標題:	Circuits and Systems.
標題:	Processor Architectures.
標題:	Electronics and Microelectronics, Instrumentation.
ISBN:	9783319220352
ISBN:	9783319220345
內容註:	1. Introduction -- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection -- 3. Analyzing the Trade-off between Different Memory Cores and Controllers -- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES -- 5. Verilog for Implementation and Verification -- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation -- 7. Conclusions.
電子資源:	http://dx.doi.org/10.1007/978-3-319-22035-2

IP cores design from specifications to production[electronic resource] :modeling, verification, optimization, and protection /
Mohamed, Khaled Salah.

IP cores design from specifications to productionmodeling, verification, optimization, and protection /[electronic resource] :by Khaled Salah Mohamed. - Cham :Springer International Publishing :2016. - ix, 154 p. :ill., digital ;24 cm. - Analog circuits and signal processing,1872-082X. - Analog circuits and signal processing..

1. Introduction -- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection -- 3. Analyzing the Trade-off between Different Memory Cores and Controllers -- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES -- 5. Verilog for Implementation and Verification -- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation -- 7. Conclusions.

ISBN: 9783319220352

Standard No.: 10.1007/978-3-319-22035-2doiSubjects--Topical Terms:

339143
Integrated circuits
--Very large scale integration.

LC Class. No.: TK7874.75 / .M64 2016

Dewey Class. No.: 621.395

IP cores design from specifications to production[electronic resource] :modeling, verification, optimization, and protection /
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490 1 $a Analog circuits and signal processing, $x 1872-082X
505 0 $a 1. Introduction -- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection -- 3. Analyzing the Trade-off between Different Memory Cores and Controllers -- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES -- 5. Verilog for Implementation and Verification -- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation -- 7. Conclusions.
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