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FPGA design[electronic resource] :be...

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Simpson, Philip Andrew.

FPGA design[electronic resource] :best practices for team-based reuse /

レコード種別:	コンピュータ・メディア : 単行資料
[NT 15000414] null:	621.395
タイトル / 著者:	FPGA design : best practices for team-based reuse // by Philip Andrew Simpson.
著者:	Simpson, Philip Andrew.
出版された:	Cham : : Springer International Publishing :, 2015.
記述:	xi, 257 p. : : ill. (some col.), digital ;; 24 cm.
主題:
国際標準図書番号 (ISBN) :	9783319179247 (electronic bk.)
国際標準図書番号 (ISBN) :	9783319179230 (paper)
[NT 15000228] null:	Introduction -- Project Management -- Design Specification -- System Modeling -- Resource Scoping -- Design Environment -- Board Design -- Power and Thermal analysis -- Team Based Design -- RTL Design -- IP reuse -- Embedded Design -- Functional verification -- Timing Closure -- High level?Design -- In System Debug -- Design Sign-off.#

FPGA design[electronic resource] :best practices for team-based reuse /
Simpson, Philip Andrew.

FPGA designbest practices for team-based reuse /[electronic resource] :by Philip Andrew Simpson. - 2nd ed. - Cham :Springer International Publishing :2015. - xi, 257 p. :ill. (some col.), digital ;24 cm.

Introduction -- Project Management -- Design Specification -- System Modeling -- Resource Scoping -- Design Environment -- Board Design -- Power and Thermal analysis -- Team Based Design -- RTL Design -- IP reuse -- Embedded Design -- Functional verification -- Timing Closure -- High level?Design -- In System Debug -- Design Sign-off.#

ISBN: 9783319179247 (electronic bk.)

Standard No.: 10.1007/978-3-319-17924-7doiSubjects--Topical Terms:

353965

LC Class. No.: TK7895.G36

Dewey Class. No.: 621.395

FPGA design[electronic resource] :best practices for team-based reuse /
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300 $a xi, 257 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Introduction -- Project Management -- Design Specification -- System Modeling -- Resource Scoping -- Design Environment -- Board Design -- Power and Thermal analysis -- Team Based Design -- RTL Design -- IP reuse -- Embedded Design -- Functional verification -- Timing Closure -- High level?Design -- In System Debug -- Design Sign-off.#
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