大葉大學圖書館 |

System-on-chip test architectures[electronic resource] :nanometer design for testability /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
杜威分類號:	621.39/5
書名/作者:	System-on-chip test architectures : nanometer design for testability // edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba.
其他作者:	Wang, Laung-Terng.
出版者:	Amsterdam ; : Morgan Kaufmann Publishers,, c2008.
面頁冊數:	xxxvi, 856 p. : : ill. ;; 25 cm.
叢書名:	The Morgan Kaufmann series in systems on silicon
標題:	Systems on a chip - Testing.
標題:	Integrated circuits - Very large scale integration
標題:	Integrated circuits - Very large scale integration
ISBN:	9780123739735
ISBN:	012373973X
書目註:	Includes bibliographical references and index.
內容註:	Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends.
摘要、提要註:	Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students.
電子資源:	An electronic book accessible through the World Wide Web; click for information
電子資源:	An electronic book accessible through the World Wide Web; click for information
電子資源:	http://www.loc.gov/catdir/toc/ecip0719/2007023373.html
電子資源:	http://www.loc.gov/catdir/enhancements/fy0808/2007023373-d.html

System-on-chip test architectures[electronic resource] :nanometer design for testability /
System-on-chip test architecturesnanometer design for testability /[electronic resource] :edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba. - Amsterdam ;Morgan Kaufmann Publishers,c2008. - xxxvi, 856 p. :ill. ;25 cm. - The Morgan Kaufmann series in systems on silicon.

Includes bibliographical references and index.

Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends.

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students.

Electronic reproduction.
Amsterdam :
Elsevier Science & Technology,
2008.

Mode of access: World Wide Web.

ISBN: 9780123739735

Source: 137803:137940Elsevier Science & Technologyhttp://www.sciencedirect.comSubjects--Topical Terms:

417281
Systems on a chip
--Testing.Index Terms--Genre/Form:

336502
Electronic books.

LC Class. No.: TK7895.E42 / S978 2008eb

Dewey Class. No.: 621.39/5

System-on-chip test architectures[electronic resource] :nanometer design for testability /
LDR:04050nam 2200385Ia 4500 001 341746
003 OCoLC
005 20090612093507.0
006 m d
007 cr cn|||||||||
008 110627s2008 ne a sb 001 0 eng d
020 $a 9780123739735
020 $a 012373973X
029 1 $a NZ1 $b 12541551
029 1 $a AU@ $b 000043178404
035 $a (OCoLC)228148482
035 $a ocn228148482
037 $a 137803:137940 $b Elsevier Science & Technology $n http://www.sciencedirect.com
040 $a OPELS $c OPELS
049 $a TEFA
050 1 4 $a TK7895.E42 $b S978 2008eb
082 0 4 $a 621.39/5 $2 22
245 0 0 $a System-on-chip test architectures $h [electronic resource] : $b nanometer design for testability / $c edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba.
260 $a Amsterdam ; $a Boston : $b Morgan Kaufmann Publishers, $c c2008.
300 $a xxxvi, 856 p. : $b ill. ; $c 25 cm.
440 4 $a The Morgan Kaufmann series in systems on silicon
504 $a Includes bibliographical references and index.
505 0 $a Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends.
520 $a Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students.
533 $a Electronic reproduction. $b Amsterdam : $c Elsevier Science & Technology, $d 2008. $n Mode of access: World Wide Web. $n System requirements: Web browser. $n Title from title screen (viewed on May 14, 2008). $n Access may be restricted to users at subscribing institutions.
650 0 $a Systems on a chip $x Testing. $3 417281
650 0 $a Integrated circuits $x Very large scale integration $x Testing. $3 417282
650 0 $a Integrated circuits $x Very large scale integration $x Design. $3 417283
655 7 $a Electronic books. $2 local $3 336502
700 1 $a Wang, Laung-Terng. $3 404402
700 1 $a Stroud, Charles E. $3 417279
700 1 $a Touba, Nur A. $3 417280
710 2 $a ScienceDirect (Online service) $3 365609
776 1 $c Original $z 9780123739735 $z 012373973X $w (DLC) 2007023373 $w (OCoLC)140109577
856 4 0 $3 ScienceDirect $u http://www.sciencedirect.com/science/book/9780123739735 $z An electronic book accessible through the World Wide Web; click for information
856 4 0 $3 Referex $u http://www.engineeringvillage.com/controller/servlet/OpenURL?genre=book&isbn=9780123739735 $z An electronic book accessible through the World Wide Web; click for information
856 4 1 $3 Table of contents only $u http://www.loc.gov/catdir/toc/ecip0719/2007023373.html
856 4 2 $3 Publisher description $u http://www.loc.gov/catdir/enhancements/fy0808/2007023373-d.html
994 $a C0 $b TEF