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Electronic design automation[electronic resource] :synthesis, verification, and test /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
杜威分類號:	621.39/5
書名/作者:	Electronic design automation : synthesis, verification, and test // edited by Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng.
其他作者:	Wang, Laung-Terng.
出版者:	Burlington, MA : : Morgan Kaufmann Publishers/Elsevier,, 2009.
面頁冊數:	1 online resource.
標題:	Electronic circuit design - Data processing.
標題:	Computer-aided design.
ISBN:	9780123743640
ISBN:	0123743648
內容註:	Ch. 1. Introduction / Charles E. Stroud, Lang-Terng Wang and Yao-Wen Chang -- Ch. 2. Fundamentals of CMOS design / Xinghao Chen and Nur A. Touba -- Ch. 3. Design for testability / Laung-Terng Wang -- Ch. 4. Fundamentals of algorithms / Chung-Yang Huang, Chao-Yue Lai and Kwang-Ting Cheng -- Ch. 5. Electronic system-level design and high-level synthesis / Jianwen Zhu and Nikil Dutt -- Ch. 6. Logic synthesis in a nutshell / Jie-Hong Jiang and Srinivas Devadas -- Ch. 7. Test synthesis / Laung-Terng Wang, Xiaoqing Wen and Shianling Wu -- Ch. 8. Logic and circuit simulation / Jiun-Lang Huang, Cheng-Kok Koh and Stephen F. Cauley -- Ch. 9. Functional verification / Hung-Pin Wen, Li-C. Wang and Kwang-Ting Cheng -- Ch. 10. Floorplanning / Tung-Chieh Chen and Yao-Wen Chang -- Ch. 11. Placement / Chris Chu -- Ch. 12. Global and detailed routing / Huang-Yu Chen and Yao-Wen Chang -- Ch. 13. Synthesis of clock ad power/ground networks / Cheng-Kok Koh, Jitesh Jain and Stephen F. Cauley.
摘要、提要註:	This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book. Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes.
電子資源:	An electronic book accessible through the World Wide Web; click for information
電子資源:	An electronic book accessible through the World Wide Web; click for information

Electronic design automation[electronic resource] :synthesis, verification, and test /
Electronic design automationsynthesis, verification, and test /[electronic resource] :edited by Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng. - Burlington, MA :Morgan Kaufmann Publishers/Elsevier,2009. - 1 online resource.

Ch. 1. Introduction / Charles E. Stroud, Lang-Terng Wang and Yao-Wen Chang -- Ch. 2. Fundamentals of CMOS design / Xinghao Chen and Nur A. Touba -- Ch. 3. Design for testability / Laung-Terng Wang -- Ch. 4. Fundamentals of algorithms / Chung-Yang Huang, Chao-Yue Lai and Kwang-Ting Cheng -- Ch. 5. Electronic system-level design and high-level synthesis / Jianwen Zhu and Nikil Dutt -- Ch. 6. Logic synthesis in a nutshell / Jie-Hong Jiang and Srinivas Devadas -- Ch. 7. Test synthesis / Laung-Terng Wang, Xiaoqing Wen and Shianling Wu -- Ch. 8. Logic and circuit simulation / Jiun-Lang Huang, Cheng-Kok Koh and Stephen F. Cauley -- Ch. 9. Functional verification / Hung-Pin Wen, Li-C. Wang and Kwang-Ting Cheng -- Ch. 10. Floorplanning / Tung-Chieh Chen and Yao-Wen Chang -- Ch. 11. Placement / Chris Chu -- Ch. 12. Global and detailed routing / Huang-Yu Chen and Yao-Wen Chang -- Ch. 13. Synthesis of clock ad power/ground networks / Cheng-Kok Koh, Jitesh Jain and Stephen F. Cauley.

This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book. Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes.

Electronic reproduction.
Amsterdam :
Elsevier Science & Technology,
2010.

Mode of access: World Wide Web.

ISBN: 9780123743640

Source: 153199:153357Elsevier Science & Technologyhttp://www.sciencedirect.comSubjects--Topical Terms:

404405
Electronic circuit design
--Data processing.Index Terms--Genre/Form:

336502
Electronic books.

LC Class. No.: TK7867 / .E4227 2009

Dewey Class. No.: 621.39/5

Electronic design automation[electronic resource] :synthesis, verification, and test /
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020 $a 0123743648
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245 0 0 $a Electronic design automation $h [electronic resource] : $b synthesis, verification, and test / $c edited by Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng.
260 $a Burlington, MA : $b Morgan Kaufmann Publishers/Elsevier, $c 2009.
300 $a 1 online resource.
505 0 $a Ch. 1. Introduction / Charles E. Stroud, Lang-Terng Wang and Yao-Wen Chang -- Ch. 2. Fundamentals of CMOS design / Xinghao Chen and Nur A. Touba -- Ch. 3. Design for testability / Laung-Terng Wang -- Ch. 4. Fundamentals of algorithms / Chung-Yang Huang, Chao-Yue Lai and Kwang-Ting Cheng -- Ch. 5. Electronic system-level design and high-level synthesis / Jianwen Zhu and Nikil Dutt -- Ch. 6. Logic synthesis in a nutshell / Jie-Hong Jiang and Srinivas Devadas -- Ch. 7. Test synthesis / Laung-Terng Wang, Xiaoqing Wen and Shianling Wu -- Ch. 8. Logic and circuit simulation / Jiun-Lang Huang, Cheng-Kok Koh and Stephen F. Cauley -- Ch. 9. Functional verification / Hung-Pin Wen, Li-C. Wang and Kwang-Ting Cheng -- Ch. 10. Floorplanning / Tung-Chieh Chen and Yao-Wen Chang -- Ch. 11. Placement / Chris Chu -- Ch. 12. Global and detailed routing / Huang-Yu Chen and Yao-Wen Chang -- Ch. 13. Synthesis of clock ad power/ground networks / Cheng-Kok Koh, Jitesh Jain and Stephen F. Cauley.
505 8 $a Ch. 14. Fault Simulation and Test Generation / James C.-M. Li and Michael S. Hsiao.
520 $a This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book. Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes.
533 $a Electronic reproduction. $b Amsterdam : $c Elsevier Science & Technology, $d 2010. $n Mode of access: World Wide Web. $n System requirements: Web browser. $n Title from title screen (viewed on Feb. 24, 2010). $n Access may be restricted to users at subscribing institutions.
650 0 $a Electronic circuit design $x Data processing. $3 404405
650 0 $a Computer-aided design. $3 197442
655 7 $a Electronic books. $2 local $3 336502
700 1 $a Wang, Laung-Terng. $3 404402
700 1 $a Chang, Yao-Wen. $3 404403
700 1 $a Cheng, Kwang-Ting, $d 1961- $3 404404
710 2 $a ScienceDirect (Online service) $3 365609
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856 4 0 $3 ScienceDirect $u http://www.sciencedirect.com/science/book/9780123743640 $z An electronic book accessible through the World Wide Web; click for information
856 4 0 $3 Referex $u http://www.engineeringvillage.com/controller/servlet/OpenURL?genre=book&isbn=9780123743640 $z An electronic book accessible through the World Wide Web; click for information
994 $a C0 $b TEF