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System on chip test architectures : ...

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Stroud Charles E. Ed.

System on chip test architectures : nanometer design for testability

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
書名/作者:	System on chip test architectures : nanometer design for testability/ Wang, Laung-Terng Ed.;Stroud, Charles E. Ed.;Touba, Nur A. Ed.
作者:	Wang Laung-Terng Ed.
其他作者:	Stroud Charles E. Ed.
出版者:	Burlington, MA : Morgan Kaufmann Publishers, 2008
面頁冊數:	856頁; 24x20公分
標題:	Systems on a chip-Testing
標題:	Integrated circuits-Very large
標題:	Integrated circuits-Very ...
ISBN:	9780123739735(精裝)

System on chip test architectures : nanometer design for testability
Wang Laung-Terng Ed.

System on chip test architectures : nanometer design for testabilityWang, Laung-Terng Ed.;Stroud, Charles E. Ed.;Touba, Nur A. Ed. - 1st ed - Burlington, MAMorgan Kaufmann Publishers2008 - 856頁24x20公分 - The Morgan Kaufmann series in systems on silicon.

ISBN: 9780123739735(精裝)新台幣1217Subjects--Topical Terms:

229609
Systems on a chip-Testing

System on chip test architectures : nanometer design for testability
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300 $a 856頁 $c 24x20公分
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700 $a Stroud Charles E. Ed. $3 229607
700 $a Touba Nur A. Ed. $3 229608

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