大葉大學圖書館 |

Instruction level parallelism[electronic resource] /

Record Type:	Language materials, printed : Monograph/item
[NT 15000414]:	004.35
Title/Author:	Instruction level parallelism/ by Alex Aiken ... [et al.].
other author:	Aiken, Alex.
Published:	Boston, MA : : Springer US :, 2016.
Description:	xxi, 255 p. : : ill., digital ;; 24 cm.
Contained By:	Springer eBooks
Subject:	Compilers (Computer programs) - Congresses.
Subject:	Parallel processing (Electronic computers) - Congresses.
Subject:	Computer Science.
Subject:	Processor Architectures.
Subject:	Communications Engineering, Networks.
Subject:	Programming Languages, Compilers, Interpreters.
Subject:	Performance and Reliability.
ISBN:	9781489977977
ISBN:	9781489977953
[NT 15000228]:	Introduction -- Overview of ILP Architectures -- Scheduling Basic Blocks -- Trace Scheduling -- Percolation Scheduling -- Modulo Scheduling -- Software Pipelining by Kernal Recognition -- Epilogue.
[NT 15000229]:	Since its introduction decades ago, Instruction Level Parallelism (ILP) has gradually become ubiquitous and is now featured in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors. Because these architectures could not exist or (in the case of superscalar machines) cannot achieve their full potential without specific sophisticated compilation techniques to exploit ILP, the development of architectures that support ILP has proceeded hand-in-hand with the development of sophisticated compiler technology, such as Trace Scheduling and Software Pipelining. While essential for achieving the full potential of ILP, in both performance as well as power consumption management, these techniques are still not widely known, in part because of their intricacy and in part because the only widely available references for ILP techniques are the primary resources, with the brevity of introduction common to conference proceedings. This book precisely formulates, and simplifies the presentation of Instruction Level Parallelism (ILP) compilation techniques. It uniquely offers consistent and uniform descriptions of the code transformations involved. Due to the ubiquitous nature of ILP in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors, this book is useful to the student, the practitioner and also the researcher of advanced compilation techniques. With an emphasis on fine-grain instruction level parallelism, this book will also prove interesting to researchers and students of parallelism at large, in as much as the techniques described yield insights that go beyond superscalar and VLIW (Very Long Instruction Word) machines compilation and are more widely applicable to optimizing compilers in general. ILP techniques have found wide and crucial application in Design Automation, where they have been used extensively in the optimization of performance as well as area and power minimization of computer designs.
Online resource:	http://dx.doi.org/10.1007/978-1-4899-7797-7

Instruction level parallelism[electronic resource] /
Instruction level parallelism[electronic resource] /by Alex Aiken ... [et al.]. - Boston, MA :Springer US :2016. - xxi, 255 p. :ill., digital ;24 cm.

Introduction -- Overview of ILP Architectures -- Scheduling Basic Blocks -- Trace Scheduling -- Percolation Scheduling -- Modulo Scheduling -- Software Pipelining by Kernal Recognition -- Epilogue.

Since its introduction decades ago, Instruction Level Parallelism (ILP) has gradually become ubiquitous and is now featured in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors. Because these architectures could not exist or (in the case of superscalar machines) cannot achieve their full potential without specific sophisticated compilation techniques to exploit ILP, the development of architectures that support ILP has proceeded hand-in-hand with the development of sophisticated compiler technology, such as Trace Scheduling and Software Pipelining. While essential for achieving the full potential of ILP, in both performance as well as power consumption management, these techniques are still not widely known, in part because of their intricacy and in part because the only widely available references for ILP techniques are the primary resources, with the brevity of introduction common to conference proceedings. This book precisely formulates, and simplifies the presentation of Instruction Level Parallelism (ILP) compilation techniques. It uniquely offers consistent and uniform descriptions of the code transformations involved. Due to the ubiquitous nature of ILP in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors, this book is useful to the student, the practitioner and also the researcher of advanced compilation techniques. With an emphasis on fine-grain instruction level parallelism, this book will also prove interesting to researchers and students of parallelism at large, in as much as the techniques described yield insights that go beyond superscalar and VLIW (Very Long Instruction Word) machines compilation and are more widely applicable to optimizing compilers in general. ILP techniques have found wide and crucial application in Design Automation, where they have been used extensively in the optimization of performance as well as area and power minimization of computer designs.

ISBN: 9781489977977

Standard No.: 10.1007/978-1-4899-7797-7doiSubjects--Topical Terms:

468934
Compilers (Computer programs)
--Congresses.

LC Class. No.: QA76.58 / .A35 2016

Dewey Class. No.: 004.35

Instruction level parallelism[electronic resource] /
LDR:03163nam a2200313 a 4500 001 476420
003 DE-He213
005 20161130052853.0
006 m d
007 cr nn 008maaau
008 181208s2016 mau s 0 eng d
020 $a 9781489977977 $q (electronic bk.)
020 $a 9781489977953 $q (paper)
024 7 $a 10.1007/978-1-4899-7797-7 $2 doi
035 $a 978-1-4899-7797-7
040 $a GP $c GP
041 0 $a eng
050 4 $a QA76.58 $b .A35 2016
072 7 $a UYF $2 bicssc
072 7 $a COM011000 $2 bisacsh
082 0 4 $a 004.35 $2 23
090 $a QA76.58 $b .I59 2016
245 0 0 $a Instruction level parallelism $h [electronic resource] / $c by Alex Aiken ... [et al.].
260 $a Boston, MA : $b Springer US : $b Imprint: Springer, $c 2016.
300 $a xxi, 255 p. : $b ill., digital ; $c 24 cm.
505 0 $a Introduction -- Overview of ILP Architectures -- Scheduling Basic Blocks -- Trace Scheduling -- Percolation Scheduling -- Modulo Scheduling -- Software Pipelining by Kernal Recognition -- Epilogue.
520 $a Since its introduction decades ago, Instruction Level Parallelism (ILP) has gradually become ubiquitous and is now featured in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors. Because these architectures could not exist or (in the case of superscalar machines) cannot achieve their full potential without specific sophisticated compilation techniques to exploit ILP, the development of architectures that support ILP has proceeded hand-in-hand with the development of sophisticated compiler technology, such as Trace Scheduling and Software Pipelining. While essential for achieving the full potential of ILP, in both performance as well as power consumption management, these techniques are still not widely known, in part because of their intricacy and in part because the only widely available references for ILP techniques are the primary resources, with the brevity of introduction common to conference proceedings. This book precisely formulates, and simplifies the presentation of Instruction Level Parallelism (ILP) compilation techniques. It uniquely offers consistent and uniform descriptions of the code transformations involved. Due to the ubiquitous nature of ILP in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors, this book is useful to the student, the practitioner and also the researcher of advanced compilation techniques. With an emphasis on fine-grain instruction level parallelism, this book will also prove interesting to researchers and students of parallelism at large, in as much as the techniques described yield insights that go beyond superscalar and VLIW (Very Long Instruction Word) machines compilation and are more widely applicable to optimizing compilers in general. ILP techniques have found wide and crucial application in Design Automation, where they have been used extensively in the optimization of performance as well as area and power minimization of computer designs.
650 0 $a Compilers (Computer programs) $v Congresses. $3 468934
650 0 $a Parallel processing (Electronic computers) $v Congresses. $3 386175
650 1 4 $a Computer Science. $3 423143
650 2 4 $a Processor Architectures. $3 463933
650 2 4 $a Communications Engineering, Networks. $3 463863
650 2 4 $a Programming Languages, Compilers, Interpreters. $3 466913
650 2 4 $a Performance and Reliability. $3 466950
700 1 $a Aiken, Alex. $3 687170
710 2 $a SpringerLink (Online service) $3 463450
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-1-4899-7797-7
950 $a Computer Science (Springer-11645)