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Design-for-test and test optimizatio...

Chakrabarty, Krishnendu.

Design-for-test and test optimization techniques for TSV-based 3D stacked ICs[electronic resource] /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
杜威分類號:	621.3815
書名/作者:	Design-for-test and test optimization techniques for TSV-based 3D stacked ICs/ by Brandon Noia, Krishnendu Chakrabarty.
作者:	Noia, Brandon.
其他作者:	Chakrabarty, Krishnendu.
出版者:	Cham : : Springer International Publishing :, 2014.
面頁冊數:	xviii, 247 p. : : ill. (some col.), digital ;; 24 cm.
Contained By:	Springer eBooks
標題:	Three-dimensional integrated circuits - Testing.
標題:	Three-dimensional integrated circuits - Design and construction.
標題:	Engineering.
標題:	Circuits and Systems.
標題:	Processor Architectures.
標題:	Semiconductors.
ISBN:	9783319023786 (electronic bk.)
ISBN:	9783319023779 (paper)
電子資源:	http://dx.doi.org/10.1007/978-3-319-02378-6

Design-for-test and test optimization techniques for TSV-based 3D stacked ICs[electronic resource] /
Noia, Brandon.

Design-for-test and test optimization techniques for TSV-based 3D stacked ICs[electronic resource] /by Brandon Noia, Krishnendu Chakrabarty. - Cham :Springer International Publishing :2014. - xviii, 247 p. :ill. (some col.), digital ;24 cm.

ISBN: 9783319023786 (electronic bk.)Subjects--Topical Terms:

613109
Three-dimensional integrated circuits
--Testing.

Dewey Class. No.: 621.3815

Design-for-test and test optimization techniques for TSV-based 3D stacked ICs[electronic resource] /
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