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Multi-net optimization of VLSI inter...

Kolodny, Avinoam.

Multi-net optimization of VLSI interconnect[electronic resource] /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
杜威分類號:	621.3815
書名/作者:	Multi-net optimization of VLSI interconnect/ by Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer.
作者:	Moiseev, Konstantin.
其他作者:	Kolodny, Avinoam.
出版者:	New York, NY : : Springer New York :, 2015.
面頁冊數:	xvi, 233 p. : : ill. (some col.), digital ;; 24 cm.
Contained By:	Springer eBooks
標題:	Interconnects (Integrated circuit technology)
標題:	Integrated circuits - Very large scale integration.
標題:	Engineering.
標題:	Circuits and Systems.
標題:	Electronics and Microelectronics, Instrumentation.
標題:	Processor Architectures.
ISBN:	9781461408215 (electronic bk.)
ISBN:	9781461408208 (paper)
內容註:	An Overview of the VLSI Interconnect Problem -- Interconnect Aspects in Design Methodology and EDA Tools -- Scaling Dependent Electrical Modeling of Interconnects -- Net-by-Net Wire Optimization -- Multi-Net Sizing and Spacing of Bundle Wires -- Multi-net Sizing and Spacing in General Layouts -- Interconnect Optimization by Net Ordering -- Layout Migration -- Future Directions in Interconnect Optimization.
電子資源:	http://dx.doi.org/10.1007/978-1-4614-0821-5

Multi-net optimization of VLSI interconnect[electronic resource] /
Moiseev, Konstantin.

Multi-net optimization of VLSI interconnect[electronic resource] /by Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. - New York, NY :Springer New York :2015. - xvi, 233 p. :ill. (some col.), digital ;24 cm.

An Overview of the VLSI Interconnect Problem -- Interconnect Aspects in Design Methodology and EDA Tools -- Scaling Dependent Electrical Modeling of Interconnects -- Net-by-Net Wire Optimization -- Multi-Net Sizing and Spacing of Bundle Wires -- Multi-net Sizing and Spacing in General Layouts -- Interconnect Optimization by Net Ordering -- Layout Migration -- Future Directions in Interconnect Optimization.

ISBN: 9781461408215 (electronic bk.)

Standard No.: 10.1007/978-1-4614-0821-5doiSubjects--Topical Terms:

417005
Interconnects (Integrated circuit technology)

LC Class. No.: TK7874.53

Dewey Class. No.: 621.3815

Multi-net optimization of VLSI interconnect[electronic resource] /
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505 0 $a An Overview of the VLSI Interconnect Problem -- Interconnect Aspects in Design Methodology and EDA Tools -- Scaling Dependent Electrical Modeling of Interconnects -- Net-by-Net Wire Optimization -- Multi-Net Sizing and Spacing of Bundle Wires -- Multi-net Sizing and Spacing in General Layouts -- Interconnect Optimization by Net Ordering -- Layout Migration -- Future Directions in Interconnect Optimization.
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