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Advanced hardware design for error correcting codes[electronic resource] /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
杜威分類號:	005.717
書名/作者:	Advanced hardware design for error correcting codes/ edited by Cyrille Chavet, Philippe Coussy.
其他作者:	Chavet, Cyrille.
出版者:	Cham : : Springer International Publishing :, 2015.
面頁冊數:	ix,192 p. : : ill. (some col.), digital ;; 24 cm.
Contained By:	Springer eBooks
標題:	Error-correcting codes (Information theory) - Congresses.
標題:	Decoders (Electronics)
標題:	Engineering.
標題:	Circuits and Systems.
標題:	Communications Engineering, Networks.
標題:	Information Systems and Communication Service.
ISBN:	9783319105697 (electronic bk.)
ISBN:	9783319105680 (paper)
內容註:	User Needs -- Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding -- Implementation of Polar Decoders -- Parallel architectures for Turbo Product Codes Decoding -- VLSI implementations of sphere detectors -- Stochastic Decoders for LDPC Codes -- MP-SoC/NoC architectures for error correction -- ASIP design for multi-standard channel decoders -- Hardware design of parallel interleaver architecture: a survey.
摘要、提要註:	This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book's chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. Examines how to optimize the architecture of hardware design for error correcting codes; Presents error correction codes from theory to optimized architecture for the current and the next generation standards; Provides coverage of industrial user needs advanced error correcting techniques.
電子資源:	http://dx.doi.org/10.1007/978-3-319-10569-7

Advanced hardware design for error correcting codes[electronic resource] /
Advanced hardware design for error correcting codes[electronic resource] /edited by Cyrille Chavet, Philippe Coussy. - Cham :Springer International Publishing :2015. - ix,192 p. :ill. (some col.), digital ;24 cm.

User Needs -- Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding -- Implementation of Polar Decoders -- Parallel architectures for Turbo Product Codes Decoding -- VLSI implementations of sphere detectors -- Stochastic Decoders for LDPC Codes -- MP-SoC/NoC architectures for error correction -- ASIP design for multi-standard channel decoders -- Hardware design of parallel interleaver architecture: a survey.

This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book's chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. Examines how to optimize the architecture of hardware design for error correcting codes; Presents error correction codes from theory to optimized architecture for the current and the next generation standards; Provides coverage of industrial user needs advanced error correcting techniques.

ISBN: 9783319105697 (electronic bk.)

Standard No.: 10.1007/978-3-319-10569-7doiSubjects--Topical Terms:

386189
Error-correcting codes (Information theory)
--Congresses.

LC Class. No.: TK5102.96

Dewey Class. No.: 005.717

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520 $a This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book's chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. Examines how to optimize the architecture of hardware design for error correcting codes; Presents error correction codes from theory to optimized architecture for the current and the next generation standards; Provides coverage of industrial user needs advanced error correcting techniques.
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