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Flip-flop design in nanometer CMOS[electronic resource] :from high speed to low energy /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
杜威分類號:	621.3815
書名/作者:	Flip-flop design in nanometer CMOS : from high speed to low energy // by Massimo Alioto, Elio Consoli, Gaetano Palumbo.
作者:	Alioto, Massimo.
其他作者:	Consoli, Elio.
出版者:	Cham : : Springer International Publishing :, 2015.
面頁冊數:	xv, 260 p. : : ill., digital ;; 24 cm.
Contained By:	Springer eBooks
標題:	Metal oxide semiconductors, Complementary - Design and construction.
標題:	Flip chip technology.
標題:	Integrated circuits - Very large scale integration
標題:	Engineering.
標題:	Circuits and Systems.
標題:	Electronic Circuits and Devices.
標題:	Processor Architectures.
標題:	Nanotechnology and Microengineering.
ISBN:	9783319019970 (electronic bk.)
ISBN:	9783319019963 (paper)
內容註:	The Logical Effort Method -- Design in the Energy-Delay Space -- Clocked Storage Elements -- Flip-Flop Optimized Design -- Analysis and Comparison in the Energy-Delay-Area Domain -- Energy Efficiency Versus Clock Slope -- Hold Time Issues and Impact of variations on Flip-Flop Topologies -- Ultra-Fast and Energy-Efficient Pulsed Latch Topologies.
摘要、提要註:	This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gain an insight into the inter-dependence of design parameters under practical constraints. This book serves as a valuable reference for practicing engineers working in the VLSI design area, and as text book for senior undergraduate, graduate and postgraduate students (already familiar with digital circuits and timing). Provides a unified treatment of Flip-Flop design and energy/variation-aware selection in nanometer CMOS VLSI systems Offers in-depth analysis of the impact of nanometer effects on design tradeoffs Presents a comprehensive analysis, by considering more than 20 topologies covering all relevant classes of circuits Uses a rigorous framework based on novel methodologies to include layout parasitics within the circuit design loop
電子資源:	http://dx.doi.org/10.1007/978-3-319-01997-0

Flip-flop design in nanometer CMOS[electronic resource] :from high speed to low energy /
Alioto, Massimo.

Flip-flop design in nanometer CMOSfrom high speed to low energy /[electronic resource] :by Massimo Alioto, Elio Consoli, Gaetano Palumbo. - Cham :Springer International Publishing :2015. - xv, 260 p. :ill., digital ;24 cm.

The Logical Effort Method -- Design in the Energy-Delay Space -- Clocked Storage Elements -- Flip-Flop Optimized Design -- Analysis and Comparison in the Energy-Delay-Area Domain -- Energy Efficiency Versus Clock Slope -- Hold Time Issues and Impact of variations on Flip-Flop Topologies -- Ultra-Fast and Energy-Efficient Pulsed Latch Topologies.

This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gain an insight into the inter-dependence of design parameters under practical constraints. This book serves as a valuable reference for practicing engineers working in the VLSI design area, and as text book for senior undergraduate, graduate and postgraduate students (already familiar with digital circuits and timing). Provides a unified treatment of Flip-Flop design and energy/variation-aware selection in nanometer CMOS VLSI systems Offers in-depth analysis of the impact of nanometer effects on design tradeoffs Presents a comprehensive analysis, by considering more than 20 topologies covering all relevant classes of circuits Uses a rigorous framework based on novel methodologies to include layout parasitics within the circuit design loop

ISBN: 9783319019970 (electronic bk.)

Standard No.: 10.1007/978-3-319-01997-0doiSubjects--Topical Terms:

418300
Metal oxide semiconductors, Complementary
--Design and construction.

LC Class. No.: TK7871.99.M44

Dewey Class. No.: 621.3815

Flip-flop design in nanometer CMOS[electronic resource] :from high speed to low energy /
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