大葉大學圖書館 |

Wafer-level chip-scale packaging[electronic resource] :analog and power semiconductor applications /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
杜威分類號:	621
書名/作者:	Wafer-level chip-scale packaging : analog and power semiconductor applications // by Shichun Qu, Yong Liu.
作者:	Qu, Shichun.
其他作者:	Liu, Yong.
出版者:	New York, NY : : Springer New York :, 2015.
面頁冊數:	xvii, 322 p. : : ill., digital ;; 24 cm.
Contained By:	Springer eBooks
標題:	Chip scale packaging.
標題:	Engineering.
標題:	Electronics and Microelectronics, Instrumentation.
標題:	Circuits and Systems.
標題:	Engineering Thermodynamics, Heat and Mass Transfer.
ISBN:	9781493915569 (electronic bk.)
ISBN:	9781493915552 (paper)
內容註:	Chapter 1. Demand and Challenges for Wafer Level Analog and Power Packaging -- Chapter 2. Fan-In Analog Wafer Level Chip Scale Package -- Chapter 3. Fan-Out Analog Wafer Level Chip Scale Package -- Chapter 4. Wafer Level Analog Chip Scale Package Stackable Design -- Chapter 5. Wafer Level Discrete Power MOSFET Package Design -- Chapter 6. Wafer Level Packaging TSV/Stack die for Integration of Analog and Power Solution -- Chapter 7. Thermal Management, Design, Analysis for WLCSP -- Chapter 8. Electrical and Multi-Physics Simulations for Analog and Power WLCSP -- Chapter 9. WLCSP Typical Assembly Process -- Chapter 10. WLCSP Typical Reliability and Test.
摘要、提要註:	This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology Introduces the development of the analog and power SIP/3D/TSV/stack die packaging technology Presents the wafer-level analog IC packaging design through fan-in and fan-out with RDLs
電子資源:	http://dx.doi.org/10.1007/978-1-4939-1556-9

Wafer-level chip-scale packaging[electronic resource] :analog and power semiconductor applications /
Qu, Shichun.

Wafer-level chip-scale packaginganalog and power semiconductor applications /[electronic resource] :by Shichun Qu, Yong Liu. - New York, NY :Springer New York :2015. - xvii, 322 p. :ill., digital ;24 cm.

Chapter 1. Demand and Challenges for Wafer Level Analog and Power Packaging -- Chapter 2. Fan-In Analog Wafer Level Chip Scale Package -- Chapter 3. Fan-Out Analog Wafer Level Chip Scale Package -- Chapter 4. Wafer Level Analog Chip Scale Package Stackable Design -- Chapter 5. Wafer Level Discrete Power MOSFET Package Design -- Chapter 6. Wafer Level Packaging TSV/Stack die for Integration of Analog and Power Solution -- Chapter 7. Thermal Management, Design, Analysis for WLCSP -- Chapter 8. Electrical and Multi-Physics Simulations for Analog and Power WLCSP -- Chapter 9. WLCSP Typical Assembly Process -- Chapter 10. WLCSP Typical Reliability and Test.

This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology Introduces the development of the analog and power SIP/3D/TSV/stack die packaging technology Presents the wafer-level analog IC packaging design through fan-in and fan-out with RDLs

ISBN: 9781493915569 (electronic bk.)

Standard No.: 10.1007/978-1-4939-1556-9doiSubjects--Topical Terms:

602638
Chip scale packaging.

LC Class. No.: TK7870.17

Dewey Class. No.: 621

Wafer-level chip-scale packaging[electronic resource] :analog and power semiconductor applications /
LDR:02827nam a2200325 a 4500 001 424629
003 DE-He213
005 20150602153329.0
006 m d
007 cr nn 008maaau
008 151119s2015 nyu s 0 eng d
020 $a 9781493915569 (electronic bk.)
020 $a 9781493915552 (paper)
024 7 $a 10.1007/978-1-4939-1556-9 $2 doi
035 $a 978-1-4939-1556-9
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7870.17
072 7 $a TJF $2 bicssc
072 7 $a TEC008000 $2 bisacsh
072 7 $a TEC008070 $2 bisacsh
082 0 4 $a 621 $2 23
090 $a TK7870.17 $b .Q1 2015
100 1 $a Qu, Shichun. $3 602637
245 1 0 $a Wafer-level chip-scale packaging $h [electronic resource] : $b analog and power semiconductor applications / $c by Shichun Qu, Yong Liu.
260 $a New York, NY : $b Springer New York : $b Imprint: Springer, $c 2015.
300 $a xvii, 322 p. : $b ill., digital ; $c 24 cm.
505 0 $a Chapter 1. Demand and Challenges for Wafer Level Analog and Power Packaging -- Chapter 2. Fan-In Analog Wafer Level Chip Scale Package -- Chapter 3. Fan-Out Analog Wafer Level Chip Scale Package -- Chapter 4. Wafer Level Analog Chip Scale Package Stackable Design -- Chapter 5. Wafer Level Discrete Power MOSFET Package Design -- Chapter 6. Wafer Level Packaging TSV/Stack die for Integration of Analog and Power Solution -- Chapter 7. Thermal Management, Design, Analysis for WLCSP -- Chapter 8. Electrical and Multi-Physics Simulations for Analog and Power WLCSP -- Chapter 9. WLCSP Typical Assembly Process -- Chapter 10. WLCSP Typical Reliability and Test.
520 $a This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology Introduces the development of the analog and power SIP/3D/TSV/stack die packaging technology Presents the wafer-level analog IC packaging design through fan-in and fan-out with RDLs
650 0 $a Chip scale packaging. $3 602638
650 1 4 $a Engineering. $3 372756
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 463474
650 2 4 $a Circuits and Systems. $3 463473
650 2 4 $a Engineering Thermodynamics, Heat and Mass Transfer. $3 463870
700 1 $a Liu, Yong. $3 468217
710 2 $a SpringerLink (Online service) $3 463450
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-1-4939-1556-9
950 $a Engineering (Springer-11647)