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Digital logic design sing Verilog[electronic resource] :coding and RTL synthesis /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
杜威分類號:	621.395
書名/作者:	Digital logic design sing Verilog : coding and RTL synthesis // by Vaibbhav Taraate.
作者:	Taraate, Vaibbhav.
出版者:	New Delhi : : Springer India :, 2016.
面頁冊數:	xxiii, 416 p. : : ill. (some col.), digital ;; 24 cm.
Contained By:	Springer eBooks
標題:	Logic design - Data processing.
標題:	Verilog (Computer hardware description language)
標題:	Engineering.
標題:	Circuits and Systems.
標題:	Electronics and Microelectronics, Instrumentation.
標題:	Logic Design.
ISBN:	9788132227915
ISBN:	9788132227892
內容註:	Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs.
摘要、提要註:	This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make it a useful read for students and hobbyists.
電子資源:	http://dx.doi.org/10.1007/978-81-322-2791-5

Digital logic design sing Verilog[electronic resource] :coding and RTL synthesis /
Taraate, Vaibbhav.

Digital logic design sing Verilogcoding and RTL synthesis /[electronic resource] :by Vaibbhav Taraate. - New Delhi :Springer India :2016. - xxiii, 416 p. :ill. (some col.), digital ;24 cm.

Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs.

This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make it a useful read for students and hobbyists.

ISBN: 9788132227915

Standard No.: 10.1007/978-81-322-2791-5doiSubjects--Topical Terms:

418007
Logic design
--Data processing.

LC Class. No.: TK7868.L6

Dewey Class. No.: 621.395

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520 $a This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make it a useful read for students and hobbyists.
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