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The power of assertions in SystemVer...
~
Cerny, Eduard.
The power of assertions in SystemVerilog[electronic resource] /
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
杜威分類號:
621.381548
書名/作者:
The power of assertions in SystemVerilog/ by Eduard Cerny ... [et al.].
其他作者:
Cerny, Eduard.
出版者:
Boston, MA : : Springer US,, 2010.
面頁冊數:
xvii, 544 p. : : ill., digital ;; 24 cm.
Contained By:
Springer eBooks
標題:
Verilog (Computer hardware description language)
標題:
Integrated circuits - Verification
標題:
Engineering.
標題:
Circuits and Systems.
標題:
Electrical Engineering.
ISBN:
9781441966001 (electronic bk.)
ISBN:
9781441965998 (paper)
電子資源:
http://dx.doi.org/10.1007/978-1-4419-6600-1
The power of assertions in SystemVerilog[electronic resource] /
The power of assertions in SystemVerilog
[electronic resource] /by Eduard Cerny ... [et al.]. - Boston, MA :Springer US,2010. - xvii, 544 p. :ill., digital ;24 cm.
ISBN: 9781441966001 (electronic bk.)Subjects--Topical Terms:
418008
Verilog (Computer hardware description language)
LC Class. No.: TK7874.58 / .P69 2010
Dewey Class. No.: 621.381548
The power of assertions in SystemVerilog[electronic resource] /
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