大葉大學圖書館 |

VLSI test principles and architectures[electronic resource] :design for testability /

Record Type:	Language materials, printed : Monograph/item
[NT 15000414]:	621.39/5
Title/Author:	VLSI test principles and architectures : design for testability // edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen.
other author:	Wang, Laung-Terng.
Published:	Amsterdam ; : Elsevier Morgan Kaufmann Publishers,, c2006.
Description:	1 online resource (xxx, 777 p.) : : ill.
Subject:	Integrated circuits - Very large scale integration
Subject:	Integrated circuits - Very large scale integration
Subject:	Circuits int�egr�es �a tr�es grande �echelle - Essais.
Subject:	Circuits int�egr�es �a tr�es grande �echelle - Conception et construction.
Subject:	TECHNOLOGY & ENGINEERING - Electronics
Subject:	TECHNOLOGY & ENGINEERING - Electronics
Subject:	COMPUTERS - Logic Design.
Subject:	Circuitos integrados vlsi.
Subject:	Integrated circuits / Very large scale integration / Testing.
Subject:	Integrated circuits / Very large scale integration / Design.
Subject:	Testen.
Subject:	VLSI.
ISBN:	9780123705976
ISBN:	0123705975
ISBN:	9780080474793 (electronic bk.)
ISBN:	0080474799 (electronic bk.)
ISBN:	6610966842 (electronic bk.)
ISBN:	9786610966844 (electronic bk.)
[NT 15000227]:	Includes bibliographical references and index.
[NT 15000228]:	Chapter 1 Introduction -- Chapter 2 Design for Testability -- Chapter 3 Logic and Fault Simulation -- Chapter 4 Test Generation -- Chapter 5 Logic Built-In Self-Test -- Chapter 6 Test Compression -- Chapter 7 Logic Diagnosis -- Chapter 8 Memory Testing and Built-In Self-Test -- Chapter 9 Memory Diagnosis and Built-In Self-Repair -- Chapter 10 Boundary Scan and Core-Based Testing -- Chapter 11 Analog and Mixed-Signal Testing -- Chapter 12 Test Technology Trends in the Nanometer Age.
[NT 15000229]:	This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.
Online resource:	http://www.sciencedirect.com/science/book/9780123705976

VLSI test principles and architectures[electronic resource] :design for testability /
VLSI test principles and architecturesdesign for testability /[electronic resource] :edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen. - Amsterdam ;Elsevier Morgan Kaufmann Publishers,c2006. - 1 online resource (xxx, 777 p.) :ill. - The Morgan Kaufmann series in systems on silicon. - Morgan Kaufmann series in systems on silicon..

Includes bibliographical references and index.

Chapter 1 Introduction -- Chapter 2 Design for Testability -- Chapter 3 Logic and Fault Simulation -- Chapter 4 Test Generation -- Chapter 5 Logic Built-In Self-Test -- Chapter 6 Test Compression -- Chapter 7 Logic Diagnosis -- Chapter 8 Memory Testing and Built-In Self-Test -- Chapter 9 Memory Diagnosis and Built-In Self-Repair -- Chapter 10 Boundary Scan and Core-Based Testing -- Chapter 11 Analog and Mixed-Signal Testing -- Chapter 12 Test Technology Trends in the Nanometer Age.

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

ISBN: 9780123705976

Source: 132281:132389Elsevier Science & Technologyhttp://www.sciencedirect.comSubjects--Topical Terms:

417282
Integrated circuits
--Very large scale integrationIndex Terms--Genre/Form:

336502
Electronic books.

LC Class. No.: TK7874.75 / .V587 2006eb

Dewey Class. No.: 621.39/5

VLSI test principles and architectures[electronic resource] :design for testability /
LDR:03223cam 2200505Ia 4500 001 370675
005 20120813091434.0
006 m d
007 cr cn|||||||||
008 121228s2006 ne a ob 001 0 eng d
019 $a 123441360 $a 154703466 $a 299750751 $a 434023516 $a 441775657 $a 648178245 $a 772045718
020 $a 9780123705976
020 $a 0123705975
020 $a 9780080474793 (electronic bk.)
020 $a 0080474799 (electronic bk.)
020 $a 6610966842 (electronic bk.)
020 $a 9786610966844 (electronic bk.)
029 1 $a NZ1 $b 12434945
029 1 $a AU@ $b 000043319312
029 1 $a DEBSZ $b 355395088
029 1 $a DEBBG $b BV039832118
029 1 $a HEBIS $b 291468322
035 $a ocn162573568
037 $a 132281:132389 $b Elsevier Science & Technology $n http://www.sciencedirect.com
040 $a OPELS $b eng $c OPELS $d OCLCG $d OCLCQ $d N$T $d EBLCP $d MERUC $d E7B $d IDEBK $d UMI $d CEF $d NHM $d DEBSZ $d KNOVL
049 $a NTYA
050 4 $a TK7874.75 $b .V587 2006eb
072 7 $a TEC $x 008050 $2 bisacsh
072 7 $a TEC $x 008030 $2 bisacsh
072 7 $a COM $x 036000 $2 bisacsh
082 0 4 $a 621.39/5 $2 22
084 $a ZN 4030 $2 rvk
084 $a ZN 4950 $2 rvk
084 $a ZN 4952 $2 rvk
245 0 0 $a VLSI test principles and architectures $h [electronic resource] : $b design for testability / $c edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen.
260 $a Amsterdam ; $a Boston : $b Elsevier Morgan Kaufmann Publishers, $c c2006.
300 $a 1 online resource (xxx, 777 p.) : $b ill.
490 1 $a The Morgan Kaufmann series in systems on silicon
504 $a Includes bibliographical references and index.
505 0 $a Chapter 1 Introduction -- Chapter 2 Design for Testability -- Chapter 3 Logic and Fault Simulation -- Chapter 4 Test Generation -- Chapter 5 Logic Built-In Self-Test -- Chapter 6 Test Compression -- Chapter 7 Logic Diagnosis -- Chapter 8 Memory Testing and Built-In Self-Test -- Chapter 9 Memory Diagnosis and Built-In Self-Repair -- Chapter 10 Boundary Scan and Core-Based Testing -- Chapter 11 Analog and Mixed-Signal Testing -- Chapter 12 Test Technology Trends in the Nanometer Age.
520 $a This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.
588 $a Description based on print version record.
650 0 $a Integrated circuits $x Very large scale integration $x Testing. $3 417282
650 0 $a Integrated circuits $x Very large scale integration $x Design. $3 417283
650 6 $a Circuits int�egr�es �a tr�es grande �echelle $x Essais. $3 486470
650 6 $a Circuits int�egr�es �a tr�es grande �echelle $x Conception et construction. $3 486471
650 7 $a TECHNOLOGY & ENGINEERING $x Electronics $x Circuits $x VLSI & ULSI. $2 bisacsh $3 486472
650 7 $a TECHNOLOGY & ENGINEERING $x Electronics $x Circuits $x Logic. $2 bisacsh $3 486473
650 7 $a COMPUTERS $x Logic Design. $2 bisacsh $3 486474
650 7 $a Circuitos integrados vlsi. $2 larpcal $3 486475
650 7 $a Integrated circuits / Very large scale integration / Testing. $2 blmsh $3 486476
650 7 $a Integrated circuits / Very large scale integration / Design. $2 blmsh $3 486477
650 0 7 $a Testen. $2 gtt $3 416768
650 0 7 $a VLSI. $2 swd $3 486478
655 4 $a Electronic books. $2 local $3 336502
700 1 $a Wang, Laung-Terng. $3 404402
700 1 $a Wu, Cheng-Wen, $c EE Ph. D. $3 486468
700 1 $a Wen, Xiaoqing. $3 486469
776 0 8 $i Print version: $t VLSI test principles and architectures. $d Amsterdam ; Boston : Elsevier Morgan Kaufmann Publishers, c2006 $z 0123705975 $z 9780123705976 $w (DLC) 2006006869 $w (OCoLC)64624834
830 0 $a Morgan Kaufmann series in systems on silicon. $3 404899
856 4 0 $3 ScienceDirect $u http://www.sciencedirect.com/science/book/9780123705976
938 $a ebrary $b EBRY $n ebr10169928
938 $a Ingram Digital eBook Collection $b IDEB $n 96684